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Install Logisim-evolution

Digital logic design tool and simulator

Install with winget
winget install --id logisim-evolution.logisim-evolution
Upgrade
winget upgrade --id logisim-evolution.logisim-evolution
Uninstall
winget uninstall --id logisim-evolution.logisim-evolution

About Logisim-evolution

Digital logic design tool and simulator

What's new in 4.1.0

- v4.1.0 (2026-02-15) - Increased number of components which may be displayed on custom circuit appearances and increased options for existing ones. - Bug fixes: - Fixed more synchronization issues with simulation tree and propagator. - Fixed INOUT port issue in TTL74245. - Fixed several other minor issues. - Enhanced TestVector for sequential circuits. See user's guide for details. - Enhanced Video resolution choices. - Allow more components to show in State (register) tab. - Enhanced Undo and Redo functionality: - Added "Undo History" dropdown menu to view and select specific undo actions. - Added "Redo History" dropdown menu to view and select specific redo actions. - Added "Clear Undo/Redo History" menu item with confirmation dialog. - Limited undo and redo history to a maximum of 64 actions. - Retained standard single-step undo and redo functionality via menu item. - Enhanced Counter component: - Counter state can now be displayed in "State" tab alongside registers. - Counter state can now drive "Assembly viewer" address. - Corrected appearance of OR gates in TikZ/SVG image exports. - Corrected font choice for default fonts in SVG image exports. - Reduced filesize of TikZ/SVG image exports. - Enhanced SoC component labels. - Enhanced Chinese localization. - Added DMA copy engine component (SocDma) in the System On Chip library.

Read release notes

Version history

Version Updated Notes
4.1.0 Unknown - v4.1.0 (2026-02-15) - Increased number of components which may be displayed on custom circuit appearances and increased options for existing ones. - Bug fixes: - Fixed more synchronization issues with simulation tree a...
4.0.0 Unknown - v4.0.0 (2025-09-07) - Updated VHDL and created Verilog generator for RAM component with byte-enables - Added VHDL and Verilog for the RAM component with line-enables - fixed clasic appearance shift-register bug - Added...
3.9.0 Unknown - Updated Java requirement to Java 21. - Added an autosave feature along with preferences for it. - Added a new preference to allow the user to choose the action keys for many functions. - Changed RAM default output from...
3.7.2 Unknown No notes